This invention relates generally to the packaging of semiconductor chips. More particularly, this invention relates to a technique for packaging different sized semiconductor chips on a common substrate.
After a semiconductor is designed, a separate package is typically designed to house the semiconductor. The reliance upon a separate package for every semiconductor design leads to expensive and time-consuming package design efforts. Accordingly, it would be highly desirable to reduce package design expenses.
A semiconductor package includes a universal substrate with interior pads, peripheral pads, and substrate traces positioned between the interior pads and the peripheral pads. The interior pads are configured for electrical interface with a first semiconductor chip. The peripheral pads are configured for electrical interface with a second semiconductor chip that is larger than the first semiconductor chip.
The invention reduces package design expenses by providing a universal package substrate that can receive semiconductor chips of different sizes. Thus, a single package can be used for a variety of devices. Preferably, the substrate connections (e.g., power pins, data pins, control pins, and the like) are universally the same, regardless of the semiconductor that is positioned within the package. The invention reduces time to market by reducing substrate design times, reducing non-recurring expenses, and reducing inventory costs.